Flash memory devices comprise a plurality of memory cells formed by complimentary metal oxide semiconductor (CMOS) transistors. Flash memory cells are typically electrically intercoupled and coupled to program and read circuitry by wordlines and bitlines. Individual wordlines and bitlines are electrically isolated one from another by dielectric, such as shallow trench isolation (STI) areas.
Technology progresses in flash memory with scaling, which increases the density of active devices (e.g., memory cells and other transistors, etc.), wordlines, bitlines, etc. Increasing memory density results in dimension reduction therein. For instance, the distance separating neighboring bitlines is reduced as memory is scaled down and the dimensions of STI and other dielectric isolating them becomes shallower and/or thinner.
During memory operation, such as programming and reading a cell, a relatively high operating voltage, such as a programming voltage VP (e.g., 5 Volts) or a read voltage VR (e.g., 0.8 Volts) is placed upon the bitline of the cell being programmed or read. Conventionally, the neighboring bitlines (e.g., the bitlines adjacent to) the bitline of the cell being programmed/read are held at a ground potential (e.g., zero Volts). Thus, during conventional memory operations, a voltage differential can exist between the bitline of the cell being operated and its neighboring bitlines.
As memory technology is scaled down, the relatively high operating voltages such as VP and VR become more significant over the reduced microscopic dimensions. Further, the decreasing distance between bitlines and the reduced dimensions of STI isolating bitlines can effectively reduce electrical isolation between bitlines. Thus, scaling down increases the possibility of transdielectric electrical interaction between neighboring bitlines as memory device technology is scaled down.
Inter-bitline leakage current is one such interaction. Inter-bitline leakage current can be driven through dielectric separating neighboring bitlines by voltage differential existing or arising between the neighboring bitlines. Inter-bitline leakage current can have undesirable effects. This leakage current can deter proper memory operations, such as programming and read.
The high voltage on the bitline connected to the cell being operated conventionally applied with the neighboring bitlines grounded cause a voltage differential (ΔV) between the bitlines. For instance, where a VP of 5 Volts is applied to the operating cell's bitline and the neighboring bitlines are grounded at zero Volts, a ΔV of 5 Volts arises. At the microscopic distances between these bitlines and/or the reduced STI dimensions that can characterize scaled down memory technology, this ΔV can be significant enough to drive a transdielectric leakage current Ilkg between these bitlines, e.g., through or underneath the STI.
The transdielectric leakage current between the operational bitline and its neighboring bitlines can effectively reduce the operating voltage on the bitline of the cell being programmed/read, and/or raise the voltage on the neighboring bitlines, connected to other cells not being operated. Reducing the programming voltage to a memory cell's bitline, such as due to leakage current with neighboring bitlines, can have the undesirable effect of misprogramming. For clarity and brevity, ‘programming’ is discussed hereinafter by way of explanation, illustration, and example. However, other memory operations such as ‘read’ are also intended to be illustrated by this discussion as well.
Misprogramming can occur where the programming voltage is inadequate to fully program a memory cell. For instance, where a fully programmed cell retains a digital ‘1’ value and an unprogrammed cell retains a digital ‘0’ value, leakage current can reduce the operating bitline voltage such that the cell being programmed does not attain the voltage value needed to fully program it. Rather than a digital ‘1’ or a digital ‘0’, the voltage value on the program cell corresponds to an indeterminate value between ‘0’ and ‘1’. Multi-level memory cells can be effected as well.
Further, where the neighboring bitlines are connected to unprogrammed cells, the leakage current driven voltage rise on those bitlines can result in erroneous or partial programming on the unprogrammed cells. For instance, where non-programmed cells retain a digital ‘0’ value and a neighboring programmed cell retains a digital ‘1’ value, leakage current can increase the bitline voltage on the non-programmed neighboring cells, such that the neighboring cells not to be programmed do not remain at a zero logical value. Rather than a digital ‘0’, the voltage value on the neighboring non-programmed cells can rise to correspond to indeterminate values between ‘0’ and ‘1’. Such misprogramming and partial programming can cause data errors such as misread cells and other memory reliability problems.
Similar problems can occur with a read operation. Undesirable leakage current between a cell to be read (e.g., applied with VR) and the neighboring cells (grounded) can result in false read results. Where the cell to be read is in a digital ‘0’ state, and one or both of the neighboring cells is (are) in a digital ‘1’ state, the inter-bitline leakage currents can erroneously render a value between the digital ‘0’ and the digital ‘1’ for the read operation.